In modern integrated circuits, semiconductor devices are formed on semiconductor substrates, and are connected through metallization layers. The metallization layers are connected to the semiconductor devices through contact plugs. Also, external pads are connected to the semiconductor devices through the contact plugs.
Typically, the formation process of contact plugs includes forming an inter-layer dielectric (ILD) over semiconductor devices, forming contact openings in the ILD, and filling a metallic material in the contact openings. However, with the increasing down-scaling of integrated circuits, the above-discussed processes experience shortcomings. While the horizontal dimensions (for example the PO-PO pitch between neighboring polysilicon lines) are continuously shrinking, the diameters of circular contact plug and the contact area between contact plugs to salicide are reduced. The thickness of the ILD is not reduced according to the same scale as the reduction of the widths of the contact plugs. Accordingly, the aspect ratios of contact plugs increase, causing the contact formation process to be more and more difficult.
The down-scaling of integrated circuits results in several problems. First, it is more and more difficult to fill the contact openings without causing voids therein. Second, the contact plugs are often in physical contact with source/drain silicide regions, hence resulting in contact resistance. The contact resistances between metals and metal silicides are typically high, however, and hence the already-high contact resistances are further worsened by the reduction in the areas of the interfaces between the contact plugs and the underlying silicide regions. Third, the process window for forming the contact openings becomes narrower and narrower. The misalignment in the formation of the contact opening may cause short circuit or open circuit, resulting in yield loss. Accordingly, the formation of contact plugs has become the bottleneck of the down-scaling of integrated circuits.